1. Field of the Invention
The present invention relates to a non-volatile semiconductor storage device including a gate-insulator-breakdown antifuse device in a memory cell.
2. Description of the Related Art
A large-capacity semiconductor memory device, an advanced semiconductor logic circuit device, and a high-performance analog circuit device each include a relatively small-capacity non-volatile semiconductor storage device to store various data. The data includes an address of a fault memory element in the large-capacity semiconductor memory device, a chip specific number necessary to manage the advanced semiconductor logic circuit device, and adjustment information to keep uniform characteristics of the high-performance analog circuit. An example of the non-volatile semiconductor storage device is a write-once device including a so-called gate-insulator-breakdown antifuse device as a memory element (see, for example, H. Ito et al. “Pure CMOS One-time Programmable Memory using Gate-OX Antifuse,” Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, PP. 469-472).
The gate-insulator-breakdown antifuse device stores data according to an electrical conductivity change due to a breakdown of the transistor's gate insulating layer. The non-volatile semiconductor storage device including the gate-insulator-breakdown antifuse device has following advantages. It needs no additional manufacturing process and is thus manufactured inexpensively. In addition, the storage device does not degrade performance of the semiconductor memory device, the semiconductor logic circuit device, and the analog circuit device that are combined on the same chip.
Information is written to and read from the gate-insulator-breakdown antifuse device as follows. During the write operation, a high voltage of about 6 V is applied to the electrodes of the gate-insulating layer. Under this condition, the gate-insulating layer locally breaks down over time, forming a weak-current path. A high voltage is further applied to the small breakdown spot to pass a relatively large current of about 2 mA. During the write operation, the breakdown spot and the vicinity thereof change in composition, forming a relatively low-resistance conductive path. The write operation is then complete.
During the read operation, a low voltage (e.g., about 1 V) is applied not to break down the antifuse device. The amount of the resulting read current is used to determine whether the stored data is zero or one.
In order for stable operation of the semiconductor memory device including the gate-insulator-breakdown antifuse device, it is important to supply, during the write operation, a sufficiently large write current to sufficiently change the composition of the gate insulating layer's breakdown spot and the vicinity thereof. The write current of about 2 mA or more is thus required.
To satisfy the requirement, the gate-insulator-breakdown antifuse device should be connected with sufficiently low resistance current paths (such as a power supply line, a signal line, a selection gate transistor connecting the memory element and the signal line, and a write buffer for driving the signal line).
An appropriate write current supplied during the writing will not lead to a large cell current during the reading in any way. The read current is centered around about 100 μA and has a large variation, and may have a nonlinear voltage-current characteristics. When, for example, 1 V is applied, the read current may be about 1 μA. A read current of 1 μA is a weak current corresponding to 1/10 to 1/100 of the read current of the memory element, such as an SRAM cell, included in other semiconductor memory devices.
This weak read current should be accepted when considering that the conductive path in the gate-insulator-breakdown antifuse device after writing operation is formed by the breakdown phenomenon. In other words, in order to rapidly and accurately determine whether the stored information is zero or one, it is important to reduce parasitic capacitance of various components such as the signal line connected to the memory element, the selection gate connecting the antifuse device and the signal line, and the sense amplifier amplifying the read small signal.
As is evident from the above description, the write characteristics may be effectively improved by increasing the signal line width and the size of the transistor included in the selection gate. In contrast, the read characteristics may be effectively improved by decreasing the signal line width and the size of the transistor included in the selection gate. In this way, in the write-once non-volatile semiconductor storage device including the gate-insulator-breakdown antifuse device as the memory element, the request for the lower resistance for the write operation and the request for the lower capacitance for the read operation are conflicting.